Affiliation:
1. Department of Electronics & Communication, Ramaiah Institute of Technology, MSR Nagar, MSRIT Post, Bangalore-560054, Karnataka, INDIA
Abstract
The capacitor-less-output-low-dropout (CLO-LDO) regulator proposed in this study can manage a wide variety of load currents. To offer temperature independent controlled LDO output, the LDO's 0.844V reference voltage is obtained using BGR, the optimized design is presented that provide full range stability, fast transient response. These benefits allow the proposed LDO regulator to operate over a wide range of operating circumstances, with very high current efficiency 99.99% and low voltage drop 100mV, operating using very low quiescent current of 0.02µA, at the output of regulator. The proposed regulator design is constructed in 90nm CMOS technology, the structure of the regulator is implemented using a Two-stage operational amplifier to obtain large DC gain 50dB to improve supply noise rejection, and a feedback loop, and exhibits better performance in terms of large phase margin 64.516 degrees with no load and 70.63degree full load.
Publisher
North Atlantic University Union (NAUN)
Subject
Electrical and Electronic Engineering,Signal Processing