A 5.6 μ A Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz

Author:

Joshi KishanORCID,Manandhar Sanjeev,Bakkaloglu Bertan

Funder

Texas Instruments, Tucson, AZ 85711 USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 27 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient;IEEE Journal of Solid-State Circuits;2024-02

2. A 0.45 mV/V Line Regulation, 0.6 V Output Voltage, Reference-Integrated, Error Amplifier-Less LDO With a 5-Transistor Regulation Core;IEEE Journal of Solid-State Circuits;2023-11

3. A CAFVF-based output-capacitor-less LDO with PSRR improvement by feed forward and negative capacitance;Integration;2023-11

4. A Low-Dropout Linear Regulator with High Power Supply Rejection;2023 16th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI);2023-10-28

5. A High-PSR High-Precision Fast-Transient-Response Capacitor-Free LDO for LiDAR Receiver SoC;2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2023-10-27

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