Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-kdielectrics for nanoscale double-gate MOSFETs-Reference-Cited by-同舟云学术

Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-kdielectrics for nanoscale double-gate MOSFETs

Published:2011-02-16 Issue:4 Volume:26 Page:045002
ISSN:0268-1242
Container-title:Semiconductor Science and Technology
language:
Short-container-title:Semicond. Sci. Technol.

Author:

Darbandy Ghader,Ritzenthaler Romain,Lime François,Garduño Ivan,Estrada Magali,Cerdeira Antonio,Iñiguez Benjamin

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference22 articles.

1. Silicon integrated circuit technology from past to future

2. Scaling CMOS: Finding the gate stack with the lowest leakage current

3. Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation

4. Analytical modeling of the gate tunneling leakage for the determination of adequate high-k dielectrics in double-gate SOI MOSFETs at the 22nm node

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