A comprehensive investigation of silicon film thickness ( T SI ) of nanoscale DG TFET for low power applications
Author:
Publisher
IOP Publishing
Subject
Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,General Materials Science
Link
https://iopscience.iop.org/article/10.1088/2043-6262/7/3/035009/pdf
Reference25 articles.
1. Low-Voltage Tunnel Transistors for Beyond CMOS Logic
2. Dielectric Modulated Tunnel Field-Effect Transistor—A Biomolecule Sensor
3. Exploring tunnel-FET for ultra low power analog applications
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1. Design and Optimization of a Heterojunction (Ge/Si) Vertical-Tunnel Field Effect Transistor (HV-TFET) with a Doped Bar for Low-Power Applications;Journal of Electronic Materials;2024-05-24
2. Analysis of the Dual Gate Vertical TFET Performance with a Dual Gate Oxide Material Stacking;2023 IEEE 3rd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC);2023-11-24
3. Electrical Noise Analysis of Z Shape Horizontal Pocket and Hetero Stack TFETs under Trap Distribution;ECS Journal of Solid State Science and Technology;2022-12-01
4. Evolution of Tunnel Field Effect Transistor for Low Power and High Speed Applications: A Review;Silicon;2022-04-08
5. Assessment of Interface Trap Charges on Proposed TFET for Low Power High-Frequency Application;Silicon;2022-01-25
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