Degradation mechanism analysis for SiC power MOSFETs under repetitive power cycling stress

Abstract

Abstract In this work, investigation on the degradation behavior of 1.2 kV/52 A silicon carbide (SiC) power MOSFETs subjected to repetitive slow power cycling stress has been performed. Electric characteristics have been characterized periodically over the stress and the respective degradation mechanisms have also been analyzed. A comprehensive degradation analysis is further conducted after the aging test by virtue of the x-ray inspection system, scanning acoustic microscope, scanning electron microscope, emission microscope, etc. Experimental results reveal that both the degradation of the gate oxide on the chip-level and the degradation of the bond wire and solder layer on the package-level have emerged over the cyclic stress. Specifically, growths of threshold voltage (V th) and gate leakage current (I gss) are thought to be relevant with the degradation of gate oxide by SiC/SiO2 interface states trapping/de-trapping electrons on the chip-level, while the appearance of fatigue in the bond wire and the delamination of the solder layer imply the degradation on the package-level. This work may provide some practical guidelines for assessments of the reliability of SiC power MOSFETs in power conversion systems.