Design and characterization of cell topology effect on SiC VDMOSFETs for high power and frequency applications

Abstract

Abstract In this paper, we present a comprehensive investigation of the impact of cell topology and pitch reduction on the DC and AC characteristics of 1200V-rated 4H-SiC planar VDMOSFETs. We have designed and fabricated four different cell topologies, namely linear, square, hexagonal, and staggered cell, in order to characterize their performance. Among the various cell types, the hexagonal cell exhibits the most favorable specific on-state resistance (Ron,sp) value. However, it is worth noting that the breakdown values of both the hexagonal and staggered square cells fall significantly below the simulated values. This is attributed to the interaction between the irregular cell boundaries and the edge cell termination region. Furthermore, we observed that the linear cell has the highest gate resistance compared to the other cell types. Additionally, the linear cell also demonstrates a lower input capacitance than the other cells. This can be attributed to its longer gate trasmission line and smaller area. Lastly, we performed dynamic double pulse tests on the fabricated VDMOSFETs to compare their switching characteristics. It was concluded that linear cell VDMOS is suitable for high switching applications, while square, hexagonal and S.S cell VDMOS are better suited for lower switching applications that require a high output current.