CMOS compatible manufacturing of a hybrid SET-FET circuit

Abstract

Abstract This study analyzes feasibility of complementary metal–oxide–semiconductor (CMOS)-compatible manufacturing of a hybrid single electron transistor–field effect transistor (SET-FET) circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar (NP) with embedded Si nanodot generated by ion-beam irradiation. The integration process from NPs to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulations taking into account parasitic effects. The FET fabrication process is adapted to meet the requirements of the pre-fabricated NPs. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.