Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices-Reference-Cited by-同舟云学术

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

Published:2021-12-11 Issue: Volume: Page:
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Container-title:2021 IEEE International Electron Devices Meeting (IEDM)
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Author:

Jagannathan H.¹,Anderson B.¹,Sohn C-W.²,Tsutsui G.¹,Strane J.¹,Xie R.¹,Fan S.¹,Kim K-I.²,Song S.²,Sieg S.¹,Seshadri I.¹,Mochizuki S.¹,Wang J.¹,Rahman A.¹,Cheon K-Y.²,Hwang I.²,Demarest J.¹,Do J.²,Fullam J.¹,Jo G.²,Hong B.²,Jung Y.²,Kim M.²,Kim S.²,Lallement R.¹,Levin T.¹,Li J.¹,Miller E.¹,Montanini P.¹,Pujari R.¹,Osborn C.¹,Sankarapandian M.¹,Son G-H.²,Waskiewicz C.¹,Wu H.¹,Yim J.²,Young A.¹,Zhang C.¹,Varghese A.¹,Robison R.¹,Burns S.¹,Zhao K.¹,Yamashita T.¹,Dechene D.¹,Guo D.¹,Divakaruni R.¹,Wu T.¹,Seo K-I.²,Bu H.¹

Affiliation:

1. IBM, IBM Research,Albany,NY,12203

2. Samsung Electronics

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720561.pdf?arnumber=9720561

Reference5 articles.

1. Vertical GAAFETs for the Ultimate CMOS Scaling

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