Optimization of double metal-gate InAs/Si heterojunction nanowire TFET-Reference-Cited by-同舟云学术

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Optimization of double metal-gate InAs/Si heterojunction nanowire TFET

Published:2020-06-22 Issue:7 Volume:35 Page:075024
ISSN:0268-1242
Container-title:Semiconductor Science and Technology
language:
Short-container-title:Semicond. Sci. Technol.

Author:

Choi Yejoo,Hong Yuri,Ko Eunah,Shin Changhwan^ORCID

Funder

IC Design Education Center

National Research Foundation of Korea

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://iopscience.iop.org/article/10.1088/1361-6641/ab8b1f/pdf

Reference23 articles.

1. Low-Voltage Tunnel Transistors for Beyond CMOS Logic

2. Atomistic Full-Band Design Study of InAs Band-to-Band Tunneling Field-Effect Transistors

3. Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers

4. InAs/Si Hetero-Junction Nanotube Tunnel Transistors

5. Modeling of High-Performance p-Type III–V Heterojunction Tunnel FETs

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance;Semiconductor Science and Technology;2024-08-07

2. A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers;Physica Scripta;2024-07-04

3. Performance improvement of SOI Tunnel-FET using pure boron and Ge pocket layer;Microelectronics Journal;2024-07

4. Design, simulation and analog/RF performance evaluation of a hetero-stacked source dual metal T-shaped gate tunnel-FET in thermally variable environments;Microsystem Technologies;2024-05-02

5. Undoped vertical dual-bilayer TFET with a super-steep sub-threshold swing: proposal and performance comparative analysis;Semiconductor Science and Technology;2023-05-23

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