Performance improvement of SOI Tunnel-FET using pure boron and Ge pocket layer-Reference-Cited by-同舟云学术

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Performance improvement of SOI Tunnel-FET using pure boron and Ge pocket layer

Published:2024-07 Issue: Volume:149 Page:106248
ISSN:1879-2391
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Baruah Karabi^ORCID,Bujar Baruah Satyabrat Malla,Baishya Srimanta

Publisher

Elsevier BV

Reference49 articles.

1. Advancement and challenges in MOSFET scaling;Ratnesh;Mater. Sci. Semicond. Process.,2021

2. Scaling the Si MOSFET: from Bulk to SOI to Bulk;Yan;IEEE Trans. Electron. Dev.,1992

3. The tunnel source (PNPN) n-MOSFET: a novel high performance transistor;Nagavarapu;IEEE Trans. Electron. Dev.,2008

4. An extended analytical approximation for the MOSFET surface potential;Chen;Solid State Electron.,2005

5. Double-gate strained-Ge Heterostructure tunneling FET (TFET) with Min, Ioff ON-state ambipolar-state simulation (quantum transport);Krishnamohan;Simulation,2008

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