Strain effect on performance of multi-stacked gate-all-around CMOS inverters-Reference-Cited by-同舟云学术

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Strain effect on performance of multi-stacked gate-all-around CMOS inverters

Published:2020-10-28 Issue:12 Volume:35 Page:125021
ISSN:0268-1242
Container-title:Semiconductor Science and Technology
language:
Short-container-title:Semicond. Sci. Technol.

Author:

Kim Kihwan,Lee Ji Hwan,Oh Saeroonter^ORCID

Funder

National Research Foundation of Korea

Hanyang University

Ministry of Trade, Industry and Energy

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://iopscience.iop.org/article/10.1088/1361-6641/abbc8e/pdf

Reference22 articles.

1. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

2. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

3. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

4. Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

5. Metrology for the next generation of semiconductor devices

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance Evaluation of Strain Effectiveness of Sub-5 nm GAA FETs with Compact Modeling based on Neural Networks;2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2023-03-07

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