The effect of passivation-layer process to amorphous InGaZnO thin-film transistors using back-channel etch method

Abstract

Abstract In this work, based on the channel damage caused by source/drain etching and passivation-layer deposition, the effects of the passivation-layer process on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) devices were studied by combining experimental investigation with simulation verification. In terms of experimental exploration, it was found that the back-channel N2O plasma treatment had a significant impact on the performance of the device, which was difficult to control. Hence, to achieve a low cost, the entire back-channel process was directly carried out as two steps of SiO x passivation-layer deposition and final thermal annealing. In the aspect of simulation verification, the influence of the passivation-layer deposition radio-frequency (RF) power and the annealing effect on the internal mechanism of the device was studied based on a high-concentration doped defect density of states (DOS) model (doping level was N D = 1020 cm−3). The experimental results demonstrated that the high-performance of an a-IGZO TFT device can be achieved by adjusting the RF power of SiO x passivation-layer deposition. It was more important that annealing after passivation-layer deposition was a critical step in the manufacture of high-performance TFTs. The device exhibited the ideal performance after annealing under 1000 W RF power, with a threshold voltage of 5.65 V, a saturation mobility of 12.87 cm2 V−1s−1, a subthreshold swing of 0.88 V dec−1, and a current on-off ratio of 2.62 × 10°8. In addition, using the DOS model, it was found that the SiO x passivation-layer process had a significant impact on the DOS distribution and the carrier distribution in the channel, which in turn caused the threshold voltage to drift. At last, the high uniformity and stability of an a-IGZO TFTs array on glass were characterized.