A Single-Ended 9T SRAM Cell With Improved Noise Margin for Low-Power Applications Used in LEDoS

Abstract

Abstract As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is a significant barrier to approaching the higher performance of microdisplay. In this paper, a new low-power SRAM cell with a single bitline is proposed to reduce the power dissipation of digital CMOS drivers. Compared with conventional differential 6T SRAM cell, the proposed 9T uses the single-ended read/write and read/write separation technology by reducing bitline and adding word lines, and write/read static noise margin (WSNM/RSNM) has been improved while the power dissipation is reduced effectively by stacking effect. When VDD is 0.8 V, the proposed cell achieves 1.4× and 2.2× improvement in WSNM and RSNM compared to D6T. Besides, the proposed cell consumes 1.4× less power during hold mode compared to D6T at VDD=0.8 V.