Author:
Zhan Yongzheng,Li Tuo,Yue Yuqiu,Liu Tongqiang,Zhou Yulong,Zou Xiaofeng
Abstract
Abstract
A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requirement of one-step structure and improving the transmission speed. In order to reduce power while achieving high data rate, multiplexing structure is also optimized by utilizing multi-frequency multi-phase technology which not only ensures the requirement of the phase stabilization, but also leaves out some flip-flops. For CMOS-CML conversion circuit, transmission gate and cross-coupled CMOS inverter are used to match the delay of CMOS inverter, suppressing the effect of common-mode noise. Simulation results show that the multiplexer works correctly and jitter of output signal is less than 0.1UI. When voltage is 1.2V, the total power is 32.7mW at 25Gb/s.
Subject
General Physics and Astronomy
Reference12 articles.
1. Effective link equalizations for serial links at 112 Gbps and beyond [C];Wu,2018
2. A survey on FEC codes for 100G and beyond optical networks [J];Tzimpragos;IEEE Communications Surveys & Tutorials,2016
3. A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS [J];Ullas;IEEE Journal of Solid-State Circuits,2014
4. A 4: 1 multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology [J];Garg;International Journal of Electronics,2020
5. A high speed and low power 4: 1 multiplexer with cascoded clock control [C];Park,2010