A 780 mW 4 $\times$ 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS

Author:

Singh Ullas,Garg Adesh,Raghavan Bharath,Huang Nick,Heng Zhang ,Zhi Huang ,Momtaz Afshin,Jun Cao

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY;Journal of Physics: Conference Series;2021-11-01

2. A 5–13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-10

3. System-Level Response of Ethernet Linkage to Bulk Current Injection into Cables;2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE;2020-09-23

4. Wireline communication: the backbone of data transfer;CSI Transactions on ICT;2020-06

5. A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology;IEICE Electronics Express;2020

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