Propagation of stacking faults from “composite” dislocation cores at low temperature in silicon nanostructures

Abstract

Abstract The unexpected occurrence of extended stacking faults in silicon nanostructures at high stress and low temperature is discussed. It is shown that those stacking faults result from the operation of “composite” dislocation core structures. It is demonstrated that such cores allow for the propagation of partial dislocations in the shuffle set with the benefit of a low Peierls stress. A classical atomistic calculation confirms indeed that shuffle partial dislocations can move under a shear stress of about 3.3 GPa (5.5% shear strain) at room temperature.