Design and analysis of 32 bit high speed carry select adder

Abstract

Abstract In the area of VLSI design, the focus is on reducing delays, power consumption and space, and improving speed. This paper presents the design of 32-bit modified-HSCSA using parallel prefix adder in which the basic design is based on Binary to Excess-1 Converter (BE1C) and also handouts brief review on traditional techniques used in standard BE1C, Brent-Kung (BK), Lander-Fischer (LF) and Kogge-Stone (KS). The performance of the presented 32 bit modified –CSA using parallel prefix adder is compared with traditional techniques and observed reduced delay. Verilog HDL is used to design the structure and the simulation and synthesis is carried out using Xilinx.