Author:
Divya Sree P.,Jyothsna Raj B.,Srinivas B.
Abstract
Abstract
Comparators play an important role in designing of SAR ADC. In this paper we achieve the required performance of SAR ADC at minimum power usage. Using of comparators will reduce the power and noise, Dynamic latch circuit used in comparator increases the speed. The differential amplifier is also discussed. Here we will get to know about Ramp ADC and also about various DAC’s like M-DAC and AUX-DAC. The time-interleaving technique is the design technique that is used to increase the speed.
Subject
General Physics and Astronomy
Reference12 articles.
1. Designing a precision comparator for 10-bit synchronization SAR ADC;Xu,2014
2. Comparator power minimization analysis for SAR ADC using multiple comparators;Ahmadi;IEEE Transactions on Circuits and Systems I: Regular Papers,2015
3. A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators;Dai,2014
4. A 0.5-V 12-bit SAR ADC using adaptive time-domain comparator with noise optimization;Hsieh;IEEE Journal of Solid-State Circuits,2018
5. An improved dynamic latch based comparator for 8-bit asynchronous SAR ADC;Bekal,2015
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Post-Silicon Validation Method for Low-Power 180 nm Dynamic Comparator in Differential 10-bit SAR ADC;2023 IEEE 9th International Conference on Smart Instrumentation, Measurement and Applications (ICSIMA);2023-10-17