A two-step routing method with wire length budgeting for PTL routing of SFQ logic circuits

Abstract

Abstract A PTL routing method for large-scale SFQ logic circuits is proposed. In this method, a routing problem is solved in two steps; global routing and detailed routing. In the global routing, a routing region is split into rectangular subregions and paths connecting them are obtained. Wire length budgeting is introduced into the global routing for allocating sufficient amount of routing resources to each net considering wire length matching in the detailed routing. In the detailed routing, exact wiring routes are determined based on a solution of the global routing and wire length matching is performed at each subregion. The global routing with wire length budgeting is formulated and an algorithm for it is proposed. In the proposed global routing algorithm, initial routes are searched at first using the rip-up and reroute technique, and then, routing resource distribution is calculated by constructing a flow-graph and solving a max-flow problem. If distribution of routing resources fails, global route extension is conducted to allocate additional routing resources to nets. The routing resource distribution and the global route extension are repeated until sufficient resources are allocated to all nets. As a design example, a 16 bit Sklansky adder was designed using the proposed method. Wire length matching in detailed routing was succeeded and the target frequency of 50 GHz was achieved.