Design and Implementation of High Speed 32-bit MAC Unit

Abstract

Abstract Due to the recent advances in VLSI technology, the need for efficient real time signal processing units have increased. The multiplier-and-accumulator (MAC) unit is the essential element of the digital signal processor. The aim is to design an 32-bit MAC unit that can perform multiplication and accumulation operation. Hence designing an effective MAC unit with reduced latency is necessary for better performance. The proposed MAC unit uses Carry-Select adder and Vedic multiplier which offers better speed (1.746 ns) in comparison with MAC unit designed using Ripple carry adder (1.782 ns). Urdhva tiryaghbyam sutra is the base sutra used in Vedic multiplier. The design was implemented in Verilog HDL using Xilinx Vivado tool and synthesis was done using Cadence Genus tool.