Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system-Reference-Cited by-同舟云学术

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Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

Published:2015-12-23 Issue:9 Volume:664 Page:092017
ISSN:1742-6588
Container-title:Journal of Physics: Conference Series
language:
Short-container-title:J. Phys.: Conf. Ser.

Author:

Ammendola R.,Biagioni A.,Frezza O.,Cicero F. Lo,Lonardo A,Martinelli M.,Paolucci P. S.,Pastorelli E.,Rossetti D.,Simula F.,Tosoratto L.,Vicini P.

Publisher

IOP Publishing

Subject

General Physics and Astronomy

Link

http://stacks.iop.org/1742-6596/664/i=9/a=092017/pdf

Reference11 articles.

1. Architectural improvements and technological enhancements for the APEnet+ interconnect system

2. The Gemini System Interconnect

3. The TH Express high performance interconnect networks

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1. Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development;Microprocessors and Microsystems;2018-09

2. The Next Generation of Exascale-Class Systems: The ExaNeSt Project;2017 Euromicro Conference on Digital System Design (DSD);2017-08

3. Bridging FPGA and GPU technologies for AO real-time control;Adaptive Optics Systems V;2016-07-27

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