Architectural improvements and technological enhancements for the APEnet+ interconnect system-Reference-Cited by-同舟云学术

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Architectural improvements and technological enhancements for the APEnet+ interconnect system

Published:2015-02-03 Issue:02 Volume:10 Page:C02005-C02005
ISSN:1748-0221
Container-title:Journal of Instrumentation
language:
Short-container-title:J. Inst.

Author:

Ammendola R.,Biagioni A.,Frezza O.,Lonardo A.,Cicero F. Lo,Martinelli M.,Paolucci P.S.,Pastorelli E.,Rossetti D.,Simula F.,Tosoratto L.,Vicini P.

Publisher

IOP Publishing

Subject

Mathematical Physics,Instrumentation

Link

http://stacks.iop.org/1748-0221/10/i=02/a=C02005/pdf

Reference12 articles.

1. APEnet+: a 3D Torus network optimized for GPU-based HPC Systems

2. QUonG: A GPU-based HPC System Dedicated to LQCD Computing

3. NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs

4. APEnet+ 34 Gbps data transmission system and custom transmission logic

5. GPU Peer-to-Peer Techniques Applied to a Cluster Interconnect

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development;Microprocessors and Microsystems;2018-09

2. The Next Generation of Exascale-Class Systems: The ExaNeSt Project;2017 Euromicro Conference on Digital System Design (DSD);2017-08

3. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system;Journal of Physics: Conference Series;2015-12-23

4. A multi-port 10GbE PCIe NIC featuring UDP offload and GPUDirect capabilities.;Journal of Physics: Conference Series;2015-12-23

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