Simulation Study of Single-Event Burnout for the 4H-SiC VDMOSFET with N+ Split Source

Abstract

Abstract Silicon Carbide (SiC) power MOSFET is the next generation device in the supply system of spacecraft. However, the current degradation or catastrophic failure of the power device could be induced when a drain voltage exceeds critical condition. In this article, an improved VDMOSFET structure for the Single-Event Burnout (SEB) is demonstrated. The improved power VDMOSFET includes a P+ shielding region at the JFET region. Meanwhile, forming a CSL layer by ion-implantation at the JFET to reduce the specific on-resistance. The device is etched in both sides to form trench and then implanting N-type impurities at the side walls of the trench to form the N+ split source (SDS-VDMOSFET). The 2-D numerical simulator Silvaco Atlas was used to study the SEB performance for the 1.2 kV-rated SiC SDS-VDMOSFET in a high linear energy transfer (LET) value of 0.5 pC/μm. The simulation results show that the improved structure can effectively reduce the peak lattice temperature induced by heavy-ion and increase the SEB threshold voltage compared with the standard VDMOSFET. Furthermore, the improved structure also presents a lower specific on-resistance. As a result, the maximum temperature of the standard VDMOSFET has exceeded 3000 K at a drain voltage of 400 V. However, the maximum temperature of the improved VDMOSFET is only 2090 K at a drain voltage of 800 V.