Abstract
Abstract
The utilization of a radiation-hard microprocessor or a System-on-Chip (SoC) design
methodology significantly benefits the future design of ASICs for HEP experiments. To evaluate the
fault tolerance of a radiation-hard design, it is important to obtain detailed information on the
soft error rate and contributing factors. This article presents a simulation-based approach to
investigate the effects of faults induced by single event transients in a microprocessor based on
the open RISC-V instruction set architecture.