Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data-Reference-Cited by-同舟云学术

Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data

Author:

Conti E.,Marconi S.,Christiansen J.,Placidi P.,Hemperek T.

Publisher

IOP Publishing

Subject

Mathematical Physics,Instrumentation

Link

Reference9 articles.

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3. First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC;2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD);2016-10

4. New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for HEP detectors at HL-LHC;2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD);2016-10

5. Performance evaluation of digital pixel readout chip architecture operating at very high rate through a reusable UVM simulation framework;2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD);2016-10