A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips-Reference-Cited by-同舟云学术

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A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

Published:2018-05-14 Issue:05 Volume:13 Page:P05018-P05018
ISSN:1748-0221
Container-title:Journal of Instrumentation
language:
Short-container-title:J. Inst.

Author:

Marconi S.,Conti E.,Christiansen J.,Placidi P.

Publisher

IOP Publishing

Subject

Mathematical Physics,Instrumentation

Link

http://stacks.iop.org/1748-0221/13/i=05/a=P05018/pdf

Reference14 articles.

1. Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

2. The RD53 collaboration's SystemVerilog-UVM simulation framework and its general applicability to design of advanced pixel readout chips

3. IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Radiation-induced effects on data integrity and link stability of the RD53A pixel readout chip;Journal of Instrumentation;2019-05-23

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