Abstract
Abstract
The High Energy Photon Source (HEPS) represents a
fourth-generation light source. This facility has made unprecedented
advancements in accelerator technology, necessitating the
development of new detectors to satisfy physical requirements such
as single-photon resolution, large dynamic range, and high frame
rates. Since 2016, the Institute of High Energy Physics has
introduced the first user-experimental hybrid pixel detector,
progressing to the fourth-generation million-pixel detector designed
for challenging conditions, with the dual-threshold single-photon
detector HEPS-Beijing PIXel (HEPS-BPIX) set as the next-generation
target. HEPS-BPIX will employ the entirely new Application-Specific
Integrated Circuit (ASIC) BP40 for pixel information readout. Data
flow will be managed and controlled through readout electronics
based on a two-tier Field-Programmable Gate Array (FPGA) system: the
Front-End Electronics (FEE) and the Input-Output Board (IOB) handle
the fan-out for 12 ASICs, and the μ4FCP is tasked with
processing serial data on high-speed links, transferring pixel-level
data to the back-end RTM and μTCA chassis, or independently
outputting through a network port, enabling remote control of the
entire detector. The new HEPS-BPIX firmware has undergone a
comprehensive redesign and update to meet the electronic
characteristics of the new chip and to improve the overall
performance of the detector. We provide an overview of the core
subunits of HEPS-BPIX, emphasizing the readout system, evaluating
the new hardware and firmware, and highlighting some of its
innovative features and characteristics.