Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy
Link
http://stacks.iop.org/1674-1056/22/i=4/a=048501/pdf
Reference18 articles.
1. A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device
2. A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer
3. A novel thin drift region device with field limiting rings in substrate
4. Compound buried layer SOI high voltage device with a step buried oxide
5. Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n + -layer
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1. Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications;Transactions on Electrical and Electronic Materials;2024-04-04
2. Reducing specific on-resistance for a trench SOI LDMOS with L-shaped P/N pillars;Results in Physics;2020-09
3. Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal–oxide–semiconductor device with high- κ insulator;Chinese Physics B;2018-04
4. Low Specific On-Resistance SOI LDMOS with Non-Depleted Embedded P-Island and Dual Trench Gate;Chinese Physics Letters;2018-03
5. An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars;Superlattices and Microstructures;2017-12
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