Simulation study of device physics and design of GeOI TFET with PNN structure and buried layer for high performance*

Author:

Wang Bin,Hu Sheng,Feng Yue,Li Peng,Hu Hui-Yong,Shu Bin

Abstract

Large threshold voltage and small on-state current are the main limitations of the normal tunneling field effect transistor (TFET). In this paper, a novel TFET with gate-controlled P+N+N+ structure based on partially depleted GeOI (PD-GeOI) substrate is proposed. With the buried P+-doped layer (BP layer) introduced under P+N+N+ structure, the proposed device behaves as a two-tunneling line device and can be shut off by the BP junction, resulting in a high on-state current and low threshold voltage. Simulation results show that the on-state current density I on of the proposed TFET can be as large as 3.4 × 10−4 A/μm, and the average subthreshold swing (SS) is 55 mV/decade. Moreover, both of I on and SS can be optimized by lengthening channel and buried P+ layer. The off-state current density of TTP TFET is 4.4 × 10−10 A/μm, and the threshold voltage is 0.13 V, showing better performance than normal germanium-based TFET. Furthermore, the physics and device design of this novel structure are explored in detail.

Publisher

IOP Publishing

Subject

General Physics and Astronomy

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