Variable-K double trenches SOI LDMOS with high-concentration P-pillar*

Abstract

A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal–oxide–semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (R on,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ⋅cm2. The R on,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.