Simulation study of high voltage GaN MISFETs with embedded PN junction*

Abstract

In this paper, we propose a new enhanced GaN MISFET with embedded pn junction, i.e., EJ-MISFET, to enhance the breakdown voltage. The embedded pn junction is used to improve the simulated device electric field distribution between gate and drain, thus achieving an enhanced breakdown voltage (BV). The proposed simulated device with L GD = 15μm presents an excellent breakdown voltage of 2050 V, which is attributed to the improvement of the device electric field distribution between gate and drain. In addition, the ON-resistance (R ON) of 15.37 Ω ⋅mm and Baliga’s figure of merit of 2.734 GW⋅cm−2 are achieved in the optimized EJ-MISFET. Compared with the field plate conventional GaN MISFET (FPC-MISFET) without embedded pn junction structure, the proposed simulated device increases the BV by 32.54% and the Baliga’s figure of merit is enhanced by 71.3%.