Research on SEE mitigation techniques using back junction and p+ buffer layer in domestic non-DTI SiGe HBTs by TCAD*

Abstract

In this paper we investigate two techniques for single event effect (SEE) mitigation by using back junction and p+ buffer layer in non-deep trench isolation (DTI) domestic silicon–germanium heterojunction bipolar transistors (SiGe HBTs) based on technology computer aided design (TCAD) simulation. The effectiveness of the two mitigation techniques and the influence of various structure parameters are investigated. Simulation results indicate that the two techniques are more effective in reducing collector charge collection induced by heavy ions striking at positions outside the collector–substrate (C–S) junction where charge collection is dominated by diffusion. By properly adjusting the parameters, charge collection of events outside the C–S junction can be reduced by more than an order of magnitude, while charge collection of events in the device center is halved without affecting the direct current (DC) and alternating current (AC) characteristics of the SiGe HBTs.