Performance assessment of symmetric double gate negative capacitance junctionless transistor with high-k spacer at elevated temperatures
Author:
Publisher
IOP Publishing
Subject
Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,General Materials Science
Link
https://iopscience.iop.org/article/10.1088/2043-6254/ab3d2e/pdf
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1. Device scaling limits of Si MOSFETs and their application dependencies
2. Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs
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4. Drain current model for nanoscale double-gate MOSFETs
5. Nanowire transistors without junctions
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