A routing algorithm for FPGAs with time-multiplexed interconnects

Author:

Luo Ruiqi,Chen Xiaolei,Ha Yajun

Abstract

Abstract Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs. In this work, we propose a time-multiplexing technique on FPGA interconnects. In order to fully exploit this interconnect architecture, we propose a time-multiplexed routing algorithm that can actively identify qualified nets and schedule them to multiplexable wires. We validate the algorithm by using the router to implement 20 benchmark circuits to time-multiplexed FPGAs. We achieve a 38% smaller minimum channel width and 3.8% smaller circuit critical path delay compared with the state-of-the-art architecture router when a wire can be time-multiplexed six times in a cycle.

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. (Q, S, R)-Dissipativity Analysis of Large-Scale Networked Systems;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-12

2. FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT;Mathematical Problems in Engineering;2022-02-07

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