An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags-Reference-Cited by-同舟云学术

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An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags

Published:2013-08 Issue:8 Volume:34 Page:085004
ISSN:1674-4926
Container-title:Journal of Semiconductors
language:
Short-container-title:J. Semicond.

Author:

Jia Xiaoyun,Feng Peng,Zhang Shengguang,Wu Nanjian,Zhao Baiqin,Liu Su

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://stacks.iop.org/1674-4926/34/i=8/a=085004/pdf

Reference10 articles.

1. RFID Handbook

2. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

3. Design of a passive UHF RFID tag for the ISO18000-6C protocol

4. A single poly EEPROM cell structure for use in standard CMOS processes

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1. Design, modelling, and simulation of a floating gate transistor with a novel security feature;Journal of Semiconductors;2020-10-01

2. Solving the integration problem of one transistor one memristor architecture with a Bi-layer IGZO film through synchronous process;Applied Physics Letters;2018-04-23

3. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications;Journal of Semiconductors;2014-05

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