Author:
Yoon Jongwoon,Kim Kwangsoo
Abstract
Abstract
A split gate MOSFET (SG-MOSFET) is widely known for reducing the reverse transfer capacitance (C
RSS). In a 3.3 kV class, the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field. In addition to the poor static performance, the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering (DIBL) caused by the high gate oxide electric field. As such, a 3.3 kV 4H-SiC split gate MOSFET with a grounded central implant region (SG-CIMOSFET) is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance. The SG-CIMOSFET has a significantly low on-resistance (R
ON) and maximum gate oxide field (E
OX) due to the central implant region. A grounded central implant region significantly reduces the C
RSS and gate drain charge (Q
GD) by partially screening the gate-to-drain capacitive coupling. Compared to a planar MOSFET, the SG MOSFET, central implant MOSFET (CIMOSFET), the SG-CIMOSFET improve the R
ON×Q
GD by 83.7%, 72.4% and 44.5%, respectively. The results show that the device features not only the smallest switching energy loss but also the fastest switching time.
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
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