Synaptic plasticity of TiO2 nanowire transistor

Abstract

Purpose The emulation of synapses is essential to neuromorphic computing systems. Despite remarkable progress has been made in the two-terminal device (memristor), three-terminal transistors evoke greater attention because of the controlled conductance between the source and drain. The purpose of this paper is to investigate the synaptic plasticity of the TiO2 nanowire transistor. Design/methodology/approach TiO2 nanowire transistor was assembled by dielectrophoresis, and the synaptic plasticity such as paired-pulse facilitation, learning behaviors and high-pass filter were studied. Findings Facilitation index decreases with the increasing pulse interval. A bigger response current is obtained at the pulses with higher amplitude and smaller intervals, which is similar to the consolidated memory at the deeply and frequently learning. The increased current at the higher stimulus frequency demonstrates a promising application in the high-pass filter. Originality/value TiO2 nanowire transistors possess broad application prospects in the future neural network.