Local damage simulations of printed circuit boards based on in‐plane cohesive zone parameters

Author:

Filipp Fuchs Peter,Fellner Klaus,Pinter Gerald

Abstract

PurposeThe purpose of this paper is to analyse, in a finite element simulation, the failure of a multilayer printed circuit board (PCB), exposed to an impact load, to better evaluate the reliability and lifetime. Thereby the focus was set on failures in the outermost epoxy layer.Design/methodology/approachThe fracture behaviour of the affected material was characterized. The parameters of a cohesive zone law were determined by performing a double cantilever beam test and a corresponding simulation. The cohesive zone law was used in an enriched finite element local simulation model to predict the crack initiation and crack propagation. Using the determined location of the initial crack, the energy release rate at the crack tip was calculated, allowing an evaluation of the local loading situation.FindingsA good concurrence between the simulated and the experimentally observed failure pattern was observed. Calculating the energy release rate of two example PCBs, the significant influence of the chosen type on the local failure behaviour was proven.Originality/valueThe work presented in this paper allows for the simulation and evaluation of failure in the outermost epoxy layers of printed circuit boards due to impact loads.

Publisher

Emerald

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering

Reference11 articles.

1. Fuchs, P.F. and Major, Z. (2010), “Cyclic bend tests for the reliability evaluation of printed circuit boards under dynamic loads”, Frattura ed Integrità Strutturale, Vol. 15 No. 15, p. 64.

2. Fuchs, P.F., Pinter, G. and Tonjec, M. (2012), “Determination of the orthotropic material properties of individual layers of printed circuit boards”, Microelectronics Reliability, Vol. 52, pp. 2723‐2730.

3. JEDEC Standard JESD22‐B111 (2003), “Board level drop test method of components for handheld electronic products”.

4. Le Coq, C., Tougui, A., Stempin, M.‐P. and Barreau, L. (2011), “Optimization for simulation of WL‐CSP subjected to drop‐test with plasticity behavior”, Microelectronics Reliability, Vol. 51 No. 6, pp. 1060‐1068.

5. Luan, J., Tee, T.Y., Pek, E., Lim, C.T. and Zhong, Z. (2007), “Dynamic responses and solder joint reliability under board level drop test”, Microelectronics Reliability, Vol. 47 Nos 2/3, pp. 450‐460.

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