Modeling and analysis of the effects of the fabrication temperatures on thermal-induced stress and speed performance of nano pMOS transistors

Abstract

Purpose The purpose of this paper is to develop and apply accurate and original models to understand and analyze the effects of the fabrication temperatures on thermal-induced stress and speed performance of nano positively doped metal oxide semiconductor (pMOS) transistors. Design/methodology/approach The speed performances of nano pMOS transistors depend strongly on the mobility of holes, which itself depends on the thermal-induced extrinsic stress σ. The author uses a finite volume method to solve the proposed system of partial differential equations needed to calculate the thermal-induced stress σ accurately. Findings The thermal extrinsic stress σ depends strongly on the thermal intrinsic stress σ0, thermal intrinsic strain ε0, elastic constants C11 and C12 and the fabrication temperatures. In literature, the effects of fabrication temperatures on C11 and C12 needed to calculate thermal-induced stress σ0 have been ignored. The new finding is that if the effects of fabrication temperatures on C11 and C12 are ignored, then, the values of stress σ0 and σ will be overestimated and, then, not accurate. Another important finding is that the speed performance of nano pMOS transistors will increase if the fabrication temperature of silicon-germanium films used as stressors is increased. Practical implications To predict correctly the thermal-induced stress and speed performance of nano pMOS transistors, the effects of fabrication temperatures on the elastic constants required to calculate the thermal-induced intrinsic stress σ0 should be taken into account. Originality/value There are three levels of originalities. The author considers the effects of the fabrication temperatures on extrinsic stress σ, intrinsic stress σ0 and elastic constants C11 and C12.