A low-cost concurrent TSV test architecture with lossless test output compression scheme

Author:

Lee Young-woo,Lim Hyunchan,Seo Sungyoul,Cho Keewon,Kang SunghoORCID

Funder

National Research Foundation of Korea

Publisher

Public Library of Science (PLoS)

Subject

Multidisciplinary

Reference37 articles.

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3. Weerasekera R, Zheng LR, Pamunuwa D, Tenhunen H. Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. IEEE/ACM International Conference on Computer-Aided Design. 2007 Nov: 212–219.

4. Chain-based approach for fast through-silicon-via coupling delay estimation;J Jang;IEEE Transactions on Very Large Scale Integration Systems,2017

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1. Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-03

2. Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-06

3. Herringbone Based TSV Architecture for Clustered Fault Repair and Aging Recovery;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021

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