Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes

Author:

Lemberski Igor,FiŜer Petr

Publisher

Elsevier BV

Subject

General Medicine

Reference18 articles.

1. Opimizing Average-Case Delay in Technology Mapping of Burst-Mode Circuits;Beerel;IEEE Int. Symp. on Advanced Research in Asynchronous Circuits and Systems,1996

2. Bernasconi, A., Ciriani, V., Luccio, F., and Pagli, L. (2008). A New Heuristic for DSOP Minimization, Proc. 8th Int. Workshop on Boolean Problems (IWSBP'08), Freiberg, Germany, 18.-19.9.2008, pp. 169-174.

3. Logic minimization algorithms for VLSI synthesis;Brayton,1984

4. Brglez, F. and Fujiwara, H. (1985). A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan, Proc. of ISCAS 1985, pp. 663-698.

5. Brglez, F., Bryan, D., and Kozminski, K. (1989). Combinational Profiles of Sequential Benchmark Circuits, Proc. of ISCAS, pp. 1929-1934.

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