Inverse-designed taper configuration for the enhancement of integrated 1 × 4 silicon photonic power splitters

Abstract

Abstract Once light is coupled to a photonic chip, its efficient distribution in terms of power splitting throughout silicon photonic circuits is very crucial. We present two types of 1 × 4 power splitters with different splitting ratios of 1:1:1:1 and 2:1:1:2. Various taper configurations were compared and analyzed to find the suitable configuration for the power splitter, and among them, parabolic tapers were chosen. The design parameters of the power splitter were determined by means of solving inverse design problems via incorporating particle swarm optimization that allows for overcoming the limitation of the intuition-based brute-force approach. The front and rear portions of the power splitters were optimized sequentially to alleviate local minima issues. The proposed power splitters have a compact footprint of 12.32 × 5 μm2 and can be fabricated through a CMOS-compatible fabrication process. Two-stage power splitter trees were measured to enhance reliability in an experiment. As a result, the power splitter with a splitting ratio of 1:1:1:1 exhibited an experimentally measured insertion loss below 0.61 dB and an imbalance below 1.01 dB within the bandwidth of 1,518–1,565 nm. Also, the power splitter with a splitting ratio of 2:1:1:2 showed an insertion loss below 0.52 dB and a targeted imbalance below 1.15 dB within the bandwidth of 1,526–1,570 nm. Such inverse-designed power splitters can be an essential part of many large-scale photonic circuits including optical phased arrays, programmable photonics, and photonic computing chips.