Author:
Praneeth Annavarapu,Immadi Govardhani,Prabhakar V. S. V.,Reddy Venkata Narayana Madhava
Abstract
Embedded micro-electro-mechanical technologies and network connectivity allow for the integration of sensing, identification, and communication capabilities into a variety of smart devices. These intelligent devices can automatically link to create the Internet of Things (IoT). The greater power consumption of a scan-based test has been one of the biggest problems since Very Large-Scale Integration (VLSI) architecture was introduced. There are too many switches made during the scan shifting procedures due to the enormous number of the scan cells. The design and implementation of an IoT access point are presented in this paper using the Logic Vision tool. In the semiconductor sector, scan chains are frequently employed for structural testing following fabrication or production. In this paper, a new architecture was designed with USB protocol, which reduces dynamic power, and fault-free circuits were constructed. The proposed architecture can work with the current one without changing the decompression architecture. Experimental findings on commercial circuits demonstrate that this strategy minimizes the scan shifting power.
Publisher
Engineering, Technology & Applied Science Research
Reference24 articles.
1. "CS301: Logic Gates," Saylor Academy. https://learn.saylor.org/mod/
2. page/view.php?id=27058.
3. E. Alpaslan, Y. Huang, X. Lin, W.-T. Cheng, and J. Dworak, "On Reducing Scan Shift Activity at RTL," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 7, pp. 1110–1120, Jul. 2010.
4. P. Girard, "Survey of low-power testing of VLSI circuits," IEEE Design & Test of Computers, vol. 19, no. 3, pp. 82–92, Jun. 2002.
5. W.-L. Li, P.-H. Wu, and J.-C. Rau, "Reducing switching activity by test slice difference technique for test volume compression," in IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, Dec. 2009, pp. 2986–2989.