Author:
Law Chong-Fatt,Yeo Kiat-Seng,Rofail Samir S.
Subject
Electrical and Electronic Engineering
Reference8 articles.
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2. Gopalan, M., Mi, Lu and Jimingyin. Design of a new compact and regular 8 × 8 multiplier using redundant binary number representation. IEEE Midwest Symposium on Circuits and Systems, Proceedings. Detroit, MI. pp.1501–1504.
3. A high-speed multiplier using a redundant binary adder tree
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