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Partial product reduction by using look-up tables for M×N multiplier

  • Published:2008-07 Issue:4 Volume:41 Page:557-571
  • ISSN:0167-9260
  • Container-title:Integration
  • language:en
  • Short-container-title:Integration

Author:

Mora-Mora Higinio,Mora-Pascual Jerónimo,Sánchez-Romero José Luis,García-Chamizo Juan Manuel

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference57 articles.

1. Design issues in high performance floating point arithmetic units, TR CSL-TR-96-711;Oberman,1996

2. Advanced Computer Arithmetic Design;Flynn,2001

3. Computer Arithmetic. Algorithms and Hardware Designs;Parhami,2000

4. SPEC Benchmark Suite Release 2/92.

5. M.A. Erle, E.M. Schwarz, M.J. Schulte, Decimal multiplication with efficient partial product generation, in: 17th IEEE Symposium on Computer Arithmetic, 2005.

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