Novel Flexible Systolic Mesh Architecture for Parallel VLSI Implementation of Finite Digital Convolution-Reference-Cited by-同舟云学术

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Novel Flexible Systolic Mesh Architecture for Parallel VLSI Implementation of Finite Digital Convolution

Published:1998-11 Issue:6 Volume:44 Page:261-266
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Mohanty B K,Meher P K

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

http://www.tandfonline.com/doi/pdf/10.1080/03772063.1998.11416054

Reference12 articles.

1. Number theoretic transforms to implement fast digital convolution

2. A V Oppenheim & R W Schafer,Digital Signal Processing.Prentice-Hall, Englewood Cliffs, NJ, 1975.

3. New algorithms for digital convolution

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3. FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic;IEEE Transactions on Signal Processing;2008-07

4. Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution;IEEE Transactions on Circuits and Systems II: Express Briefs;2006-08

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