Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style-Reference-Cited by-同舟云学术

Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style

Published:2013-08-28 Issue:10 Volume:101 Page:1357-1374
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Nikoubin Tooraj,Grailoo Mahdieh,Li Changzhi

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

http://www.tandfonline.com/doi/pdf/10.1080/00207217.2013.832389

Reference26 articles.

1. Low power multipliers based on new hybrid full adders

2. Agarwal, S., Pavankumar, V. K. & Yokesh, R. (2008). Energy-efficient high performance circuits for arithmetic units.21st International Conference on VLSI Design (VLSID 2008). 371–76.

3. Aguirre, M. & Linares, M. (2005). A low-power bootstrapped CMOS full adder.2nd Int. Conf. on Electrical and Electronics Engineering (ICEEE’05) held jointly with XI Conf. on Electrical Engineering (CIE’05) Mexico City, 243–246.

4. CMOS Full-Adders for Energy-Efficient Arithmetic Applications

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3. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-01