Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications
Author:
Affiliation:
1. Electrical & Electronics Engineering Department, Birla Institute of Technology and Science, Pilani, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2019.1692245
Reference17 articles.
1. Exploring Hybrid STT-MTJ/CMOS Energy Solution in Near-/Sub-Threshold Regime for IoT Applications
2. A review of emerging non-volatile memory (NVM) technologies and applications
3. A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory
4. Self-Terminated Write-Assist Technique for STT-RAM
5. STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique
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1. Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01
2. A Spintronic 2M/7T Computation-in-Memory Cell;Journal of Low Power Electronics and Applications;2022-12-06
3. A Variation Tolerant Nanoscale SRAM for Low Power Wireless Sensor Nodes;Wireless Personal Communications;2022-01-17
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