Energy-efficient CMOS delay line with self-supply modulation for low-power SAR ADCs
Author:
Affiliation:
1. Institute of Electrodynamics and Microelectronics (ITEM), University of Bremen, Bremen, Germany
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2019.1661024
Reference9 articles.
1. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
2. A 990-$\mu\hbox{W}$ 1.6-GHz PLL Based on a Novel Supply-Regulated Active-Loop-Filter VCO
3. A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step
4. Current starved delay element with symmetric load
5. A low-voltage, low-power CMOS delay element
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A full input range, 1–1.8 V voltage supply scalable analog voltage comparator in 180nm CMOS;International Journal of Electronics;2021-02-27
2. Noise shaping in SAR ADC;Facta universitatis - series: Electronics and Energetics;2020
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