A low power test pattern generation for built-in self-test based circuits
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2010.538899
Reference13 articles.
1. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes
2. Multiple-output low-power linear feedback shift register design
3. Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size
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1. BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture;Journal of Circuits, Systems and Computers;2018-02-06
2. On the Generation of SIC Pairs in Optimal Time;IEEE Transactions on Computers;2015-10-01
3. Reducing Test Power and Improving Test Effectiveness for Logic BIST;JSTS:Journal of Semiconductor Technology and Science;2014-10-30
4. Generation of Single Input Change Test Sequences for Conformance Test of Programmable Logic Controllers;IEEE Transactions on Industrial Informatics;2014-08
5. Pattern Generation Research of BIST Based on Low Power;Applied Mechanics and Materials;2014-03
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